Publications

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. HyperTEE a Decoupled TEE Architecture With Secure Enclave Management. The IEEE/ACM International Symposium on Microarchitecture (MICRO), Accepted, 2024.

. SecPaging Secure Enclave Paging With Hardware Enforced Protection Against Controlled Channel Attacks. ACM/IEEE The Design Automation Conference (DAC-61), Accepted, 2024.

. EnTurbo Accelerate Confidential Serverless Computing via Parallelizing Enclave Startup Procedure. ACM/IEEE The Design Automation Conference (DAC-61), Accepted, 2024.

. Elastic MSM a Fast Elastic and Modular Preprocessing Technique for Multi Scalar Multiplication Algorithm on GPUs. IACR Transactions on Cryptographic Hardware and Embedded Systems (CHES), 2024.

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. Fster NTRU Based Bootstrapping Less Than 4ms. lACR Transactions on Cryptographic Hardware and Embedded Systems (CHES), 2024.

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. FakeGuard a Novel Accelerator Architecture for Deepfake Detection Networks. proceedings of Euro-Par, to be appeared, 2024.

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. A Hybrid Sparse Dense Denfensive DNN Accelerator Architecture Against Adversarial Example Attacks. ACM Transactions on Embedded Computing Systems (TECS), 2024.

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. EnsGuard a Novel Acceleration Framework for Adversarial Ensemble Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.

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. SpecFL an Efficient Speculative Federated Learning System for Tree Based Model Training. 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024.

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. ChaosINTC: A Secure Interrupt Management Mechanism against Interrupt Based Attacks on TEE. The 60th Design Automation Conference (DAC-60), 2023.

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. TensorFHE Achieving Practical Computation on Encrypted Data Using GPGPU. IEEE International Symposium on High Performance Computer Architecture (HPCA-29), 2023.

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. HE Booster an Efficient Polynomial Arithmetic Acceleration on GPUs for Fully Homomorphic Encryption. IEEE Transactions on PARALLEL and DISTRIBUTED SYSTEMS (TPDS), 2023.

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. LAK a Low Overhead Lock and Key Based Schema for GPU Memory Safety. IEEE International Conference on Computer Design (ICCD-40), 2022.

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. Architecting the Auto Cuckoo Filter to Defend Against Cross Core Cache Attacks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022.

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. CPP a Lightweight Memory Page Management Extension to Prevent Code Pointer Leakage. Journal of Systems Architecture (JSA), 2022.

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. Conditional Address Propagation: An Efficient Defense Mechanism against Transient Execution Attacks. The 59th Design Automation Conference (DAC-59), 2022.

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. HyBP Hybrid Isolation Randomization Secure Branch Predictor. IEEE International Symposium on High Performance Computer Architecture (HPCA-28), 2022.

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. Punchcard: A Practical Red-Zone Based Scheme for Low-Overhead Heap Protection . The 23rd IEEE International Conference on High Performance Computing and Communications (HPCC-23), IEEE Outstanding Paper Award, 2021.

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. A Novel Probabilistic Saturating Counter Design for Secure Branch Predictor. Journal of Computer Science and Technology (JCST), APPT 2021 Best Paper Award, 2021.

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. Secure Hybrid Replacement Policy Mitigating Conflict Based Cache Side Channel Attacks. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), 2021.

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. NASGuard a Novel Accelerator Architecture for Robust NAS Networks. The 48th IEEE/ACM International Symposium on Computer Architecture (ISCA-48), 2021.

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. A Lightweight Isolation Mechanism for Secure Branch Predictors. The 58th Design Automation Conference (DAC-58), 2021.

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. PiPoMonitor: Mitigating Cross-Core Cache Attacks Using the Auto-Cuckoo Filter. Design, Automation And Test in Europe (DATE), 2021.

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. Mitigating Cross-Core Cache Attacks via Suspicious Traffic Detection. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021.

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. 基于边界检测的安全数据预取方案. 信息安全学报（已录用）, 2020.

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. Exploiting Security Dependence for Conditional Speculation against Spectre Attacks. IEEE Transactions on Computers (TC), 2020.

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. Enabling Rack-scale Confidential Computing using Heterogeneous Trusted Execution Environment. IEEE Symposium on Security and Privacy (S&P), 2020.

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. RCecker: A Lightweight Rule Based Mechanism for Backward Control Flow Integrity. ACM International Conference on Computing Frontiers(CF-17), 2020.

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. DNNGuard: An Elastic Heterogeneous DNN Accelerator Architecture against Adversarial Attacks. Proceedings of the 25th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-25), 2020.

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. Capturing and Obscuring Ping-Pong Patterns to Mitigate Continuous Attacks. Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2020.

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. SNA: A Siamese Network Accelerator to Exploit the Model-Level Parallelism of Hybrid Network Structure. Proceedings of the Conference on Design, Automation and Test in Europe(DATE), 2020.

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. Built-in Security Computer: Deploying Security-First Architecture Using Active Security Processor. Special Issue on Hardware Security, IEEE Transations on Computers (TC), 2020.

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. NPUFort: A Secure Architecture of DNN Accelerator Against Model Inversion Attack. Proceedings of the 2019 ACM International Conference on Computing Frontier, 2019.

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. CacheGuard: A Security-Enhanced Directory Architecture Against Continuous Attacks. Proceedings of the 2019 ACM International Conference on Computing Frontier, 2019.

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. Venice: An Effective Resource Sharing Architecture for Data Center Servers. ACM Transactions on Computer Systems(TOCS), 2019.

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. Conditional Speculation: An Effective Approach to Safeguard Out-of-Order Execution Against Spectre Attacks. IEEE International Symposium on High Performance Computer Architecture (HPCA-25), 2019.

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. 松耦合数据中心架构远程数据访问加速机制研究. 全国体系结构年会（ACA 2018）会议最佳论文奖, 2018.

. 基于硬件的代码复用攻击防御机制综述. 高技术通讯，vol. 28, no. 4, pp. 299-312, 2018.

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. RAGuard: An efficient and user-transparent hardware mechanism against ROP attacks. ACM Transactions on Architecture and Code Optimization (TACO), 2018.

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. Stateful Forward-Edge CFI Enforcement with Intel MPX. 全国体系结构年会（ACA 2018）, CCIS 908, pp. 1–16, 2018. (EI), 2018.

. Security-first Architecture: Deploying Physically Isolated Active Security Processors for Safeguarding the Future of Computing. Cybersecur 1(2), 2018.

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. RAGuard: A Hardware Based Mechanism for Backward-Edge Control-Flow Integrity. Proceedings of the ACM International Conference on Computing Frontiers, 2017.

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. Venice: Exploring Server Architectures for Effective Resource Sharing. Proceedings of the 22nd International Symposium on High-Performance Computer Architecture (HPCA-22), 2016.

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. Using Remote Memory in Data Center with PCIe Fabric. Efficient Data Center Server workshop, held in conjunction with the 19th International Symposium on High-Performance Computer Architecture (HPCA-19), 2013.

. Cost Effective Data Center Servers. Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA-19), 2013.

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. Cross-node Virtual Machine Communication Acceleration. ACM International Conference on Computing Frontiers, 2013.

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. Micro-architectural Characterization of Desktop Cloud Workloads. IEEE International Symposium on Workload Characterization (IISWC), 2012.

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. Efficient data streaming with on-chip accelerators: Opportunities and challenges. Proceedings of the 17th International Symposium on High-Performance Computer Architecture (HPCA-17), 2011.

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. Application-driven Energy-efficient Architecture Explorations for Big Data. First Workshop on Architectures and Systems for Big Data (ASBD 2011), co-held with Held in conjunction with the Twentieth International Conference on Parallel Architectures and Compilation Techniques(PACT), 2011.

. Optimization of Stateful Hardware Acceleration in Hybrid Architectures. Design, Automation and Test in Europe (DATE), 2011.

. Frequent Instruction Sequential Pattern Mining in Hardware Sample Data. IEEE International Conference on Data Mining (ICDM), 2010.

. Compiler and Runtime Techniques for Software Transactional Memory Optimization. Concurr. Comput. : Practice and Experience, 2009.

. Hardware Transactional Memory System for Parallel Programming. IEEE Asia-Pacific Computer Systems Architecture Conference (ACSAC), 2008.

. Accelerating Sequential Programs On Chip Multiprocessors Via Dynamic Prefetching Thread. Microprocessor and Microsystem, Elsevier publishing, 2007.

. A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors. Euro-Par, 2006.

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. High Performance General-Purpose Microprocessors: Past and Future. Journal of Computer Science & Technology, 2006.

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. A Memory Bandwidth Effective Cache Store Miss Policy. Asia-Pacific Computer Systems Architecture Conference 2005: 750-760, 2005.